EDN

Implementing floating-point DSP on FPGAs

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
TechRepublic

Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources ...
The Next Platform

FPGAs Focal Point for Efficient Neural Network Inference

Over the last couple of years, we have focused extensively on the hardware required for training deep neural networks and other machine learning algorithms. Focal points have included the use of ...
The Next Platform

Research Codes a Next Frontier for FPGA Systems

FPGAs might be the next big thing for a growing host of workloads in high performance and enterprise computing, but for smaller companies, not to mention research institutions, the process of ...
Electronic Design

FPGAs Get A Performance/Reliability Lift From The Bumps

According to Altera it will be the first company to use fine-pitch copper, bump-based packaging technology for commercial purposes. The technology, patented by the Taiwan Semiconductor Manufacturing ...
Hexus

Intel boasts of an FPGA chip capable of 10 TFLOPS

In a newsroom post a few hours ago Intel boasted of a new chip on the block that is capable of 10 TFLOPS. The Intel Stratix 10 FPGA can perform 10 trillion floating point operations per second, claims ...
Electronic Design

Embedded FPGA Optimized for Machine Learning and Communication

1. Processor performance is starting to level off. (Source: “Computer Architecture: A Quantitative Approach,” by John L. Hennessy and David A. Patterson) What’s not shown in the chart is where GPGPUs ...